The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a technique effective for application to a chip size package (CSP) in which bump electrodes disposed in an area on a chip and bonding pads are electrically connected to each other through Cu interconnections.
In a process of manufacturing a high-speed LSI which operates at a high frequency, it is indispensable to adopt a low-resistant interconnection material and an insulating film material having a low dielectric constant to reduce electric resistance in an interconnection and capacity between interconnections. Since Cu has low electric resistance which is about two third of that of Al and has high EM (electromigration) resistance, Cu is being used more and more for a high speed logic LSI, a microcomputer, and the like which need a low-resistant fine interconnection.
A Cu interconnection is formed by what is called the Damascene process of burying a Cu film in a groove or a through hole formed in an insulating film for the reason such that a photoresist having excellent etch selectivity has not been developed yet. When the Cu film is buried, plating, sputtering, or the like is used. Since it is requested to bury a Cu film in a groove or a through hole having a high aspect ratio to form a fine interconnection, plating having excellent burying characteristics is more advantageous than sputtering.
Cu has, however, the following problems. (a) Cu has oxidation resistance lower than that of Al. Oxidation progresses to the inside of an interconnection by heat or the like generated at the time of depositing an insulating interlayer, and electric resistance increases. (b) Cu has low strength of bonding to an insulating material including oxygen such as silicon oxide or polyimide resin. (c) Cu is easily diffused into silicon and a silicon oxide. When Cu is in contact with a diffusion layer of the substrate, the characteristics of a device deteriorate. In the process of manufacturing an LSI using Cu as a material of an interconnection, countermeasures against those problems are necessary.
Japanese Unexamined Patent Application No. Hei 4(1992)-309229 discloses a technique of covering the surfaces (top and under faces and both sides) of a Cu-based interconnection with a thin oxidation preventing layer to prevent oxidation of the Cu-based interconnection, to prevent diffusion of Cu into silicon and a silicon oxide, and to improve adhesion to a silicon oxide film. The oxidation preventing layer is made of an oxide or nitride stabler than a Cu oxide, such as a refractory metal silicide containing free silicon, an alloy of Cu and another metal or silicon, or refractory metal nitride.
Japanese Unexamined Patent Application No. Hei 5(1993)-102318 discloses a technique such that, when a plug made of a Cu alloy is formed in a connection hole (via) opened in an insulating layer containing oxygen, a thin layer made of an oxide of the alloy element (for example, chromium oxide or aluminum oxide) on a top face of the Cu alloy plug and a contact face with the insulating layer containing oxygen. The thin film layer functions as an adhesion layer, diffusion barrier for preventing the diffusion of Cu, and also as a surface protective layer to provide the Cu alloy with corrosion resistance.
Japanese Unexamined Patent Application No. Hei 9(1997)-36115 discloses a technique of forming a Cu interconnection in a groove by forming a plurality of grooves at predetermined intervals in an insulating interlayer, depositing a Cu thin film on the insulating interlayer so as to bury the grooves, and removing the Cu thin film on the insulating interlayer by chemical mechanical polishing (CMP) or the like. To reduce parasitic capacity between Cu interconnections, the insulating interlayer in which grooves are formed is made of a photosensitive polyimide resin having a lower dielectric constant than that of silicon oxide or silicon nitride. A thin Cr layer as a metal underlayer of the Cu interconnection is formed on the bottom and side walls of the groove. By the Cr layer, close adhesion between the Cu interconnection and the photosensitive polyimide resin is assured, and the oxidation of the contact face with the silicon oxide film as an underlayer, of the Cu interconnection is prevented.
The inventors of the present invention are now developing a process for manufacturing a high speed LSI by a fine design rule of 0.2 xcexcm or smaller. To improve the operating speed of the chip, the high speed LSI employs the flip chip bonding by which the distance between a connection terminal on the outside of a chip to a mother board can be made shortest. The high speed LSI also adopts an area array structure in which bump electrodes serving as external connection terminals are arranged in a central area on a chip.
The area array structure has an advantage such that a number of pins can be arranged more easily as compared with a structure (peripheral structure) in which bump electrodes are arranged on bonding pads arranged in the peripheral area of the chip. In the area array structure in which a wider space can be assured between neighboring bump electrodes, a larger diameter of the bump electrode can be allowed. Consequently, stress which occurs due to a difference between a coefficient of thermal expansion of the chip and that of the mother board can be lessened by the bump electrodes, so that the reliability of connection of the chip is increased.
To manufacture an LSI having the area array structure, interconnections for connecting bonding pads arranged in the peripheral portion of the chip and bump electrodes arranged in the whole surface of the chip, what is called re-arrangement interconnections are necessary. In the case of an LSI in which emphasis is placed on high-speed operation, it is desirable to make the re-arrangement interconnections of Cu for the above-described reasons.
It is also desirable to form the re-arrangement interconnections in a wafer process (pre-process) more than in an assembling process (post-process) which is performed after a wafer is diced into chips. Specifically, formation of the re-arrangement interconnections and the following formation of bump electrodes is performed in the wafer process, after that, a wafer is divided into a plurality of chips, and chip size packages (CSP) are formed. In such a manner, the package assembling process (post-process) becomes unnecessary. Thus, a CSP adapted to a high packing density and high-speed operation can be manufactured at low cost and in a short period of development.
The inventors examined processes as follows to manufacture a CSP in which bump electrodes arranged in an area on the chip and bump electrodes are electrically connected via the re-interconnections of Cu.
First, in a manner similar to a normal wafer process, semiconductor elements are formed on the principal face of a wafer, a plurality of interconnections (signal interconnections and power source interconnections) are formed on the semiconductor elements, and a passivation film is formed on the uppermost interconnection. The passivation film is a closely-packed insulating film such as a silicon nitride film (or a stacked film of a silicon nitride film and a silicon oxide film) formed by plasma CVD, and functions as a surface protective film for preventing intrusion by moisture and a foreign matter into an integrated circuit from the wafer surface.
Subsequently, a polyimide resin layer is formed on the passivation film, the polyimide resin layer and the passivation film under the polyimide resin layer are etched to expose a part of the uppermost interconnection, thereby forming a bonding pad. The bonding pads are arranged along the peripheral portion of the chip area defined on the principal face of the wafer.
A Cu film is deposited by sputtering on the polyimide resin layer and the bonding pads to thereby form a feeder layer. A photoresist film formed on the feeder layer is exposed and developed, thereby forming a long groove having one end extending on the bonding pad and the other end extending in a bump electrode connection area.
Subsequently, the Cu interconnection is formed by electrolytic plating on the inside of the long groove formed in the photoresist film, and a metal film made of Ni, Cr, or the like is formed on the Cu interconnection by electrolytic plating. The metal film functions as a metal underlayer of the bump electrode to be connected onto the Cu interconnection in a later process.
The photoresist film is removed, the feeder layer which becomes unnecessary is removed by etching using the Cu interconnection as a mask, a polyimide resin film is spin-coated on the Cu interconnection, and heat treatment (pre-baking) is performed to volatilize a solvent in the polyimide resin film.
A photoresist film in which a bump electrode connection area is opened is formed as an upper layer of the polyimide resin film. The polyimide resin film is removed by etching using the photoresist film as a mask to expose the Cu interconnection, thereby forming a pad.
The photoresist film is removed, heat treatment (post-baking) of 350xc2x0 C. to 400xc2x0 C. is performed to cure the polyimide resin film, and bump electrodes are connected onto the pad. After that, the wafer is diced into a plurality of chips, thereby completing CSPs.
In the CSP employing the area array structure, however, since the bump electrodes disposed in the center area of the chip are electrically connected to the bonding pads arranged in the peripheral portion of the chip via the Cu interconnections, in the center area of the chip, a plurality of Cu interconnections are routed between the bump electrodes at high density. Consequently, in the case of manufacturing a CSP by the process as described above, in the step of performing the heat treatment (post-baking) on the polyimide resin film formed on the Cu interconnections, there is the possibility that the Cu interconnections are short-circuited.
The cause of the short circuit can be considered that a carboxyl group in a polyimide precursor existing in the polyimide resin which is not cured yet is coupled with Cu in the interconnection at the time of cure, thereby causing diffusion of Cu. Usually, the diffusion of Cu as described above does not occur in the cured polyimide resin. In the case where the Cu interconnections are disposed apart from each other, no problem occurs even when Cu is diffused into the polyimide resin near the Cu interconnection. When a CSP having a number of pins or a shrunk chip size adopts the area array structure, a plurality of Cu interconnections are disposed very close to each other. Consequently, a short circuit occurs more frequently when a process as described above is employed.
An object of the invention is therefore to provide a technique capable of preventing a short circuit in Cu interconnections caused by heat treatment in a manufacturing step in a CSP in which bump electrodes disposed in an area on a chip and bonding pads are electrically connected to each other via the Cu interconnections, and realizing a CSP adapted to high-packing-density mounting and high-speed operation.
Another object of the invention is to provide a technique capable of shortening the process of manufacturing a CSP in which bump electrodes arranged in an area on a chip and bonding pads are electrically connected to each other via Cu interconnections.
The above and other objects and novel features of the invention will become apparent from the description of the specification and the accompanying drawings.
In the invention disclosed in the application, a representative mode will be briefly described as follows.
In a semiconductor device of the invention, a Cu interconnection and a polyimide resin layer covering the Cu interconnection are formed on an insulating film covering an uppermost interconnection of a chip on which a semiconductor element as a component of an integrated circuit and a predetermined number of interconnections are formed, one end of the Cu interconnection is electrically connected to a bonding pad formed by opening the insulating film to expose a part of the uppermost interconnection, and a bump electrode is connected to a pad formed by opening the polyimide resin layer to expose the other end of the Cu interconnection. A barrier layer for preventing Cu from being diffused into the polyimide resin layer is formed on the surface of the Cu interconnection.
A method of manufacturing a semiconductor device according to the invention includes the following steps of:
(a) forming a semiconductor element as a component of an integrated circuit and a predetermined number of interconnections on a principal face of a wafer and forming an insulating film on an uppermost interconnection;
(b) forming a bonding pad by opening said insulating film to expose a part of said uppermost interconnection;
(c) forming a long groove of which one end extends over said bonding pad and of which other end extends in a bump electrode connection region by forming a photoresist film over said insulating film and also said bonding pad and thereafter exposing and developing said photoresist film;
(d) forming a Cu interconnection in said long groove formed in said photoresist film;
(e) removing said photoresist film and, after that, covering the surface of said Cu interconnection with a barrier layer;
(f) forming a pad by forming a polyimide resin layer over said Cu interconnection on which said barrier layer is formed, and opening said polyimide resin layer in said bump electrode connection region to expose a part of said Cu interconnection;
(g) curing said polyimide resin layer by heating; and
(h) connecting a bump electrode onto said pad.
According to the invention, by covering the surface of the Cu interconnection with the barrier layer, a short circuit in the Cu interconnections caused by a heat treatment in a manufacturing process can be prevented.